1. Technical Field
The invention relates generally to microelectronic fabrication, and more particularly, to a method of using porous silicon for transistor isolation formation and a related structure.
2. Background
Traditional scaling of silicon-germanium (SiGe) hetero-junction bipolar transistors (HBTs) has two parts: vertical scaling and lateral scaling. FIG. 1 shows a conventional HBT 10 including an intrinsic base region 12, an extrinsic base region 14, a collector region 16, isolation regions 18 and an emitter 20. Vertical scaling typically involves changing the thickness, germanium profile, and dopant profile of intrinsic base region 12. Lateral scaling typically involves reducing collector 16 width to reduce collector 16 to base 12, 14 capacitance, which is a major parasitic component limiting maximum power gain frequency Fmax of HBT 10. Unfortunately, conventional lateral scaling cannot carry device performance much further than currently achievable. More specifically, when HBT 10 is scaled laterally, collector 16 narrows, which creates less overlap between intrinsic base 12 and collector 16. This structure disadvantageously results in reduced parasitic collector 16 to base 12 capacitance Ccb. Unfortunately, the overlap area between intrinsic base 12 and extrinsic base 14 is also reduced. The reduction of overlap area between extrinsic base 14 and intrinsic base 12 creates a very narrow region for electrons to flow, and therefore increases base resistance Rb dramatically. Since maximum frequency Fmax is dependent on the resistance-to-capacitance (RC) time constant of RbCcb, little or no net increase in Fmax is observed.
It should be recognized that the above-description is a simplified explanation of the scaling problem. However, the ideal case remains that base resistance Rb and collector-to-base capacitance Ccb should be minimized. However, achieving this ideal case requires two structural situations that are difficult to accommodate simultaneously. That is, to achieve the minimum base resistance Rb, a large overlap area between intrinsic base 12 and extrinsic base 14 is required. In contrast, to achieve the minimum collector-to-base capacitance Ccb, a small overlap area between intrinsic base 12 and collector 16 is required.
With a traditional HBT 10 it is difficult to create both structures simultaneously, and achieve maximum device performance. In particular, when forming HBT 10, it is typical to create isolation regions 18 such as shallow trench isolations (STI) that insulate the base region 12, 14 and collector 16. Trench isolations 18 are usually formed using some type of silicon oxide. When epitaxially growing intrinsic base 12, the base grows as a single crystal on any exposed single crystal silicon, i.e., over collector 16, and grows as polysilicon on any non-single crystal silicon region, i.e., over trench isolations 18. Hence, it grows as polysilicon over trench isolation 18. Polysilicon has higher resistance than comparably doped crystalline silicon, contributing to higher Rb. In HBTs 10, this creates a very narrow single crystal intrinsic base 12 and large polysilicon extrinsic base 14, which creates a high base resistance Rb and negatively affects device performance.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art that will permit simultaneous reduction of the parasitic collector-to-base capacitance Ccb and base resistance Rb.